* Chapter 1: Expert assistance in digital circuit design * Chapter 2: Use of a theorem prover for transformational synthesis * Chapter 3: An overview of high level synthesis technologies for digital ASICs * Chapter 4: Simulated annealing based synthesis of fast discrete cosine transform blocks * Chapter 5: Knowledge based expert systems in testing and design for testability - an overview * Chapter 6: Knowledge based test strategy planning * Chapter 7: HIT: a hierarchical integrated test methodology * Chapter 8: Use of fault augmented functions for automatic test pattern generation * Chapter 9: Macro-test: a VLSI testable-design technique * Chapter 10: An expert systems approach to analogue VLSI layout * Chapter 11: Guaranteeing optimality in a gridless router using AI techniques
* Chapter 1: Expert assistance in digital circuit design * Chapter 2: Use of a theorem prover for transformational synthesis * Chapter 3: An overview of high level synthesis technologies for digital ASICs * Chapter 4: Simulated annealing based synthesis of fast discrete cosine transform blocks * Chapter 5: Knowledge based expert systems in testing and design for testability - an overview * Chapter 6: Knowledge based test strategy planning * Chapter 7: HIT: a hierarchical integrated test methodology * Chapter 8: Use of fault augmented functions for automatic test pattern generation * Chapter 9: Macro-test: a VLSI testable-design technique * Chapter 10: An expert systems approach to analogue VLSI layout * Chapter 11: Guaranteeing optimality in a gridless router using AI techniques
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