As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances.
As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances.
Woorham Bae received the B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively. In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior SerDes Engineer with Ayar Labs, Santa Clara, CA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, nonvolatile memory systems, and agile hardware design methodology. Dr. Bae received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, and the IEEE Solid-State Circuits Society STG Award in 2015.
Inhaltsangabe
* Chapter 1: Introduction * Chapter 2: Introduction to phase noise and jitter * Chapter 3: CMOS oscillators * Chapter 4: Phase noise theory for CMOS oscillators * Chapter 5: Introduction to PLL/DLL * Chapter 6: PLL loop dynamics and jitter * Chapter 7: DLL loop dynamics and jitter * Chapter 8: Phase noise suppression techniques 1: subsampling PLL * Chapter 9: Phase noise suppression techniques 2: all-digital PLL * Chapter 10: Phase noise suppression techniques 3: injection locking * Chapter 11: Phase noise suppression techniques 4: clock multiplying DLL * Appendix A: Figure of merits (FoMs) for evaluating VCOs and PLLs * Appendix B: Survey on state-of-the-art clock generators * Appendix C: System Verilog modeling of CMOS clock generator including jitter * Appendix D: Noise sources in MOSFET transistor
