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This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.

Produktbeschreibung
This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.
Autorenporträt
K.N. Vijeyakumar hat seinen Master of Engineering in Angewandter Elektronik an der GCT in Coimbatore abgeschlossen. Er hat seine Forschung im Bereich CMOS-Prozessordesign für Signal- und Bildverarbeitungsanwendungen abgeschlossen. Er hat Forschungsarbeiten in mehr als 27 Fachzeitschriften und auf 50 Konferenzen in den Bereichen Prozessordesign und Design von Bild- und Signalverarbeitungsanwendungen veröffentlicht.