Andere Kunden interessierten sich auch für
![Leakage currents in MOS transistor]( "Leakage currents in MOS transistor")
Leakage currents in MOS transistor24,99 €![Digital Circuits Using Subthreshold Leakage Power Reduction Techniques]( "Digital Circuits Using Subthreshold Leakage Power Reduction Techniques")
Digital Circuits Using Subthreshold Leakage Power Reduction Techniques33,99 €![Impact of Leakage Power Reduction Techniques on Parametric Yield]( "Impact of Leakage Power Reduction Techniques on Parametric Yield")
Impact of Leakage Power Reduction Techniques on Parametric Yield45,99 €![Microwave Ovens Leakage Reduction using Band-Reject Filter]( "Microwave Ovens Leakage Reduction using Band-Reject Filter")
Microwave Ovens Leakage Reduction using Band-Reject Filter33,99 €![High Efficiency RF to DC Converter with reduced leakage current]( "High Efficiency RF to DC Converter with reduced leakage current")
High Efficiency RF to DC Converter with reduced leakage current36,99 €![1 Bit Full Adder Cell for reducing low leakage current]( "1 Bit Full Adder Cell for reducing low leakage current")
1 Bit Full Adder Cell for reducing low leakage current32,99 €![Implementation of Image Segmentation Using MATLAB]( "Implementation of Image Segmentation Using MATLAB")
Implementation of Image Segmentation Using MATLAB45,99 €
In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractorcircuits using microwind tool.