Design and Architecture for Signal and Image Processing

18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025, Proceedings
Herausgegeben:Lorandel, Jordane; Kamaleldin, Ahmed

• Broschiertes Buch

Produktbeschreibung

This book constitutes the refereed conference proceedings of the 18th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2025, held in Barcelona, Spain, during January 20-22, 2025.

The 10 full papers included in this book were carefully reviewed and selected from 23 submissions.They were organized in topical sections as follows: Specialized Hardware Architecture for Efficient Processing; Efficient Processing using AI for Image, Vision and Signal Applications, and Analysis of Emerging Techniques for Signal Processing Applications.

Produktdetails

• Lecture Notes in Computer Science 15569
• Verlag: Springer / Springer Nature Switzerland / Springer, Berlin
• Artikelnr. des Verlages: 978-3-031-87896-1
• Seitenzahl: 152
• Erscheinungstermin: 1. April 2025
• Englisch
• Abmessung: 235mm x 155mm x 9mm
• Gewicht: 242g
• ISBN-13: 9783031878961
• ISBN-10: 3031878965
• Artikelnr.: 73366365

Inhaltsangabe

.- Specialized Hardware Architecture for Efficient Processing.
.- CSD-Driven Speedup in RISC-V Processor.
.- Efficient FPGA implementation of ViT Non-Linear Functions.
.- LiFT: Lightweight,FPGA-tailored 3D object detection based on LIDAR data.
.- Efficient Processing using AI for Image, Vision and Signal Applications.
.- A practical HW-Aware NAS flow for AI vision applications on embedded heterogeneous SoCs.
.- Endoscopy image classification for wireless cpasules with CNNs on microcontroller-based platforms.
.- Joint Underwater Depth Estimation and Dehazing from Single Image using Attention U-Net.
.- KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition.
.- Analysis of Emerging Techniques for Signal Processing Applications.
.- Novel scheduling and shifter networks for 5G LDPC decoders.
.- Comparison Between In-core Hardware IDS, Off-core Hardware IDS and Software IDS.
.- Comparative Study of Memory Optimization Techniques for Dataflow-modeled Applications.