Design and Verification of ALU Using Verilog and Python Cocotb - Patel, Arpita
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This book presents a comprehensive study on the design and functional verification of an Arithmetic Logic Unit (ALU) using a hybrid approach that combines Verilog HDL for hardware modeling and Python Cocotb for testbench automation. It demonstrates how open-source tools such as Icarus Verilog, GTKWave, and Cocotb can be effectively integrated to create a professional-grade verification environment.The work provides step-by-step insights into RTL design, simulation workflows, Makefile automation, and waveform analysis, making it valuable for students, researchers, and professionals in VLSI and…mehr

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Produktbeschreibung
This book presents a comprehensive study on the design and functional verification of an Arithmetic Logic Unit (ALU) using a hybrid approach that combines Verilog HDL for hardware modeling and Python Cocotb for testbench automation. It demonstrates how open-source tools such as Icarus Verilog, GTKWave, and Cocotb can be effectively integrated to create a professional-grade verification environment.The work provides step-by-step insights into RTL design, simulation workflows, Makefile automation, and waveform analysis, making it valuable for students, researchers, and professionals in VLSI and digital system design. By merging traditional HDL design with modern Python-based verification, this book highlights an innovative path toward efficient, flexible, and scalable digital hardware verification.
Autorenporträt
Arpita Patel is an Associate Professor in the Department of Electronics and Communication Engineering at Charotar University of Science and Technology (CHARUSAT), with over 17 years of academic and research experience. Her expertise lies in VLSI and mixed-signal circuit design, FPGA-based system development, and digital verification methodologies.