Realization of Memory Fault Tolerance using Error Correcting Codes - S. Murti Sarma, N.;Lavanya, Poluboyina;Prasad Acharya, Gobinda
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This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.

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Produktbeschreibung
This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.
Autorenporträt
N.S. Murti Sarma e Ch.Sathyanarayana são professores do Instituto Sreenidhi de Ciência e Tecnologia, Yamnampet de Medchal, no estado de Telangana. K.Sandhya rani foi investigadora de VLSI e sistemas incorporados. Todos os autores têm o crédito de várias publicações.