With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective…mehr
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.
Artikelnr. des Verlages: B978-0-12-374343-5.X1000-3
Seitenzahl: 336
Erscheinungstermin: 1. September 2008
Englisch
Abmessung: 243mm x 197mm x 25mm
Gewicht: 854g
ISBN-13: 9780123743435
ISBN-10: 0123743435
Artikelnr.: 23816758
Herstellerkennzeichnung
Libri GmbH
Europaallee 1
36244 Bad Hersfeld
gpsr@libri.de
Autorenporträt
Vasilis F. Pavlidis received the B.Sc. and M.Eng. degrees in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2003 and 2008, respectively. He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer. Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative.
Inhaltsangabe
Chapter 1. Introduction Chapter 2. Manufacturing of 3-D Packaged SystemsChapter 3. 3-D Integrated Circuit Fabrication Technologies Chapter 4. Interconnect Prediction Models Chapter 5. Physical Design Techniques for 3-D ICsChapter 6. Thermal Management Techniques Chapter 7. Timing Optimization for Two-Terminal Interconnects Chapter 8. Timing Optimization for Multi-Terminal Interconnects Appendix A: Enumeration of Gate Pairs in a 3-D IC Appendix B: Formal Proof of Optimum Single Via Placement Appendix C: Proof of the Two-Terminal Via Placement HeuristicAppendix D: Proof of Condition for Via Placement of Multi-Terminal Nets References
Chapter 1. Introduction Chapter 2. Manufacturing of 3-D Packaged SystemsChapter 3. 3-D Integrated Circuit Fabrication Technologies Chapter 4. Interconnect Prediction Models Chapter 5. Physical Design Techniques for 3-D ICsChapter 6. Thermal Management Techniques Chapter 7. Timing Optimization for Two-Terminal Interconnects Chapter 8. Timing Optimization for Multi-Terminal Interconnects Appendix A: Enumeration of Gate Pairs in a 3-D IC Appendix B: Formal Proof of Optimum Single Via Placement Appendix C: Proof of the Two-Terminal Via Placement HeuristicAppendix D: Proof of Condition for Via Placement of Multi-Terminal Nets References
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