Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis (eBook, PDF)

• Format: PDF

Produktbeschreibung

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

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Produktdetails

• Verlag: Springer US
• Seitenzahl: 170
• Erscheinungstermin: 22. Oktober 2011
• Englisch
• ISBN-13: 9781461408727
• Artikelnr.: 37352516

Inhaltsangabe

Introduction; Related work; Background; Statistical Regression Based Power Models; Statistical Regression Based Power Models for FPGAs; High Level Simulation Directed RTL Power Estimation; Applying Verification Collaterals for Accurate Power Estimation; Architectural Selection using High Level Synthesis; Power Reduction using High-Level Clock-gating; Model-Checking to exploit Sequential Clock-Gating; Power model to facilitate aggressive reduction; Coprocessor Design Space Exploration using High Level Synthesis.