Prakash Rashinkar, Peter Paterson, Leena Singh

System-on-a-Chip Verification (eBook, PDF)

Methodology and Techniques

• Format: PDF

Produktbeschreibung

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

This exciting new book will be of interest to all designers and test professionals.

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Produktdetails

• Verlag: Springer US
• Seitenzahl: 372
• Erscheinungstermin: 8. Mai 2007
• Englisch
• ISBN-13: 9780306469954
• Artikelnr.: 44175851

Inhaltsangabe

System-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.