Qiaoyan Yu, Paul Ampadu

Transient and Permanent Error Control for Networks-on-Chip (eBook, PDF)

• Format: PDF

Produktbeschreibung

This book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.

• Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics;
• Provides analysis of error control in various network-on-chip layers, as well as presentation of an innovative multi-layer error control coding technique;
• Presents state-of-the-art solutions to address simultaneously reliability, energy and performance;
• Describes configurable error management solutions and their hardware implementation details for variable noise conditions;
• Provides details of a flexible and parallel NoC simulator and corresponding simulation setup to achieve the reported results.

---

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Produktdetails

• Verlag: Springer New York
• Seitenzahl: 160
• Erscheinungstermin: 18. November 2011
• Englisch
• ISBN-13: 9781461409625
• Artikelnr.: 37340496

Inhaltsangabe

Introduction.- Error Control for Transient Errors.- Error Management for Intermittent and Permanent Errors.- Datalink-Layer Adaptive Error Control.- Datalink-Network Dual-Layer Error Control.- Transient and Permanent Error Co-Management.- Flexible and Parallel Simulator for NoC with Error Control.- Conclusions.